Partial reconfiguration (PR) is an FPGA feature that allows the modification of certain parts of an FPGA while the rest of the\r\nsystem continues to operate without disruption. This distinctive characteristic of FPGAs has many potential benefits but also\r\nchallenges. The lack of good CAD tools and the deep hardware knowledge requirement result in a hard-to-use feature. In this\r\npaper, the new partition-based Xilinx PR flow is used to incorporate PR within our MPI-based message-passing framework to\r\nallow hardware designers to create template bitstreams, which are predesigned, prerouted, generic bitstreams that can be reused\r\nfor multiple applications. As an example of the generality of this approach, four different applications that use the same template\r\nbitstream are run consecutively, with a PR operation performed at the beginning of each application to instantiate the desired\r\napplication engine. We demonstrate a simplified, reusable, high-level, and portable PR interface for X86-FPGA hybrid machines.\r\nPR issues such as local resets of reconfigurable modules and context saving and restoring are addressed in this paper followed by\r\nsome examples and preliminary PR overhead measurements.
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